View SM320C6201BGLP_9075296.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

sgus031 april 2000 1 post office box 1443 ? houston, texas 772511443 highest performance fixed-point digital signal processor (dsp) sm/smj320c6201b 5-, 6.7-ns instruction cycle time 150 and 200-mhz clock rate eight 32-bit instructions/cycle 1200 and 1600 mips velociti ? advanced very long instruction word (vliw) 'c62x cpu core eight independent functional units: six alus (32-/40-bit) two 16-bit multipliers (32-bit results) load-store architecture with 32 32-bit general-purpose registers instruction packing reduces code size all instructions conditional instruction set features byte-addressable (8-, 16-, 32-bit data) 32-bit address range 8-bit overflow protection saturation bit-field extract, set, clear bit-counting normalization 1m-bit on-chip sram 512k-bit internal program/cache (16k 32-bit instructions) 512k-bit dual-access internal data (64k bytes) organized as two blocks for improved concurrency 32-bit external memory interface (emif) glueless interface to synchronous memories: sdram and sbsram glueless interface to asynchronous memories: sram and eprom four-channel bootloading direct-memory-access (dma) controller with an auxiliary channel 16-bit host-port interface (hpi) access to entire memory map two multichannel buffered serial ports (mcbsps) direct interface to t1/e1, mvip, scsa framers st-bus-switching compatible up to 256 channels each ac97-compatible serial peripheral interface (spi) compatible (motorola ? ) two 32-bit general-purpose timers flexible phase-locked loop (pll) clock generator ieee-1149.1 (jtag 2 ) boundary-scan compatible 429-pin bga package (glp suffix) cmos technology 0.18- m m/5-level metal process 3.3-v i/os, 1.8-v internal please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. velociti is a trademark of texas instruments incorporated. motorola is a trademark of motorola, inc. 2 ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture. copyright ? 2000, texas instruments incorporated /&'. "+!0)#*/ !+*/'*. '*$+-)/'+* !0--#*/ . +$ ,0 ('!/'+* "/# -+"0!/. !+*$+-) /+ .,#!'$'!/'+*. ,#- /&# /#-). +$ #2. *./-0)#*/. ./*"-" 1--*/3 -+"0!/'+* ,-+!#..'*% "+#. *+/ *#!#..-'(3 '*!(0"# /#./'*% +$ (( ,-)#/#-. glp 429-pin ball grid array (bga) package (bottom view) 20 21 19 18 16 15 17 13 11 10 12 14 w y aa v t u p m n r 8 7 6 4 5 l j k g e f h 3 2 d b c a 1 9 * ,-+"0!/. !+),('*/ /+ 44
(( ,-)#/#-. -# /#./#" 0*(#.. +/&#-1'.# *+/#" * (( +/&#- ,-+"0!/. ,-+"0!/'+* ,-+!#..'*% "+#. *+/ *#!#..-'(3 '*!(0"# /#./'*% +$ (( ,-)#/#-.

sgus031 april 2000 2 post office box 1443 ? houston, texas 772511443 description the 320c6201b dsp is a member of the fixed-point dsp family in the 320c6000 platform. the sm/smj320c6201b ('c6201b) device is based on the high-performance, advanced velociti very-long-instruction-word (vliw) architecture developed by texas instruments (ti ? ), making this dsp an excellent choice for multichannel and multifunction applications. with performance of up to 1600 million instructions per second (mips) at a clock rate of 200 mhz, the 'c6201b offers cost-effective solutions to high-performance dsp programming challenges. the 'c6201b is a newer revision of the 'c6201. the 'c6201b dsp possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. this pr ocessor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. the eight functional units provide six arithmetic logic units (alus) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. the 'c6201b can produce two multiply-accumulates (macs) per cycleefor a total of 400 million macs per second (mmacs). the 'c6201b dsp also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. the 'c6201b includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. program memory consists of a 64k-byte block that is user-configurable as cache or memory-mapped program space. data memory of the 'c6201b consists of two 32k-byte blocks of ram for improved concurrency. the peripheral set includes two multichannel buffered serial ports (mcbsps), two general-purpose timers, a host-port interface (hpi), and a glueless external memory interface (emif) capable of interfacing to sdram or sbsram and asynchronous peripherals. the 'c6201b has a complete set of development tools which includes: a new c compiler, a third-party ada 95 compiler, an assembly optimizer to simplify programming and scheduling, and a windows ? debugger interface for visibility into source code execution. device characteristics table 1 provides an overview of the 'c62x dsp. the table shows significant features of each device, including the capacity of on-chip ram, the peripherals, the execution time, and the package type with pin count. table 1. characteristics of the 'c6201b processor characteristics description device number 320c6201b on-chip memory 512-kbit program memory 512-kbit data memory (organized as two blocks) peripherals 2 multichannel buffered serial ports (mcbsps) 2 general-purpose timers host-port interface (hpi) external memory interface (emif) cycle time 6.7 ns (320c6201b 150 mhz), 5 ns (320c6201b 200 mhz) package type 27 mm 27 mm, 429-pin ceramic d-bga (glp) nominal voltage 1.8 v core 3.3 v i/o ti is a trademark of texas instruments incorporated. windows is a registered trademark of the microsoft corporation.

sgus031 april 2000 3 post office box 1443 ? houston, texas 772511443 functional block diagram emif timers interrupt selector mcbsps hpi control dma control emif control host-port interface pll power down boot- config. peripheral bus controller dma controller data memory data memory controller cpu program memory controller program memory/cache

sgus031 april 2000 4 post office box 1443 ? houston, texas 772511443 cpu description the cpu fetches velociti advanced very-long instruction words (vliw) (256 bits wide) to supply up to eight 32-bit instructi ons to the eight functional units during every clock cycle. the velociti vliw architecture features controls by which all ei ght units do not have to be supplied with instructions if they are not ready to execute. the first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. fetch packets are always 256 bits wide; however, the execute packets can vary in size. the variable-length execute packets are a key memory-saving feature, distinguishing the 'c62x cpu from other vliw architectures. the cpu features two sets of functional units. each set contains four units and a register file. one set contains functional units .l1, .s1, .m1, and .d1; the other set contains units .d2, .m2, .s2, and .l2. the two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. the two sets of functional units, along with two register files, compose sides a and b of the cpu (see figure 1 and figure 2). the four functional units on each side of the cpu can freely share the 16 registers belonging to that side. additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. while register access by functional units on the same side of the cpu as the register file can service all the units in a single clock cycle, register access using the register file across the cpu supports one read and one write per cycle. another key feature of the 'c62x cpu is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). two sets of data-addressing units (.d1 and .d2) are responsible for all data transfers between the register files and the memory. the data address driven by the .d units allows data addresses generated from one register file to be used to load or store data to or from the other register file. the 'c62x cpu supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. all instructions are conditional, and most can access any one of the 32 registers. some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically atrueo). the two .m functional units are dedicated for multiplies. the two .s and .l functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. the processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. the 32-bit instructions destined for the individual functional units are alinkedo together by a1o bits in the least significant bit (lsb) position of the instructions. the instructions that are achainedo together for simultaneous execution (up to eight in total) compose an execute packet. a a0o in the lsb of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. if an execute packet crosses the fetch packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with nop instructions. the number of execute packets within a fetch packet can vary from one to eight. execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. after decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. while most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. all load and store instructions are byte-, half-word, or word-addressable.

sgus031 april 2000 5 post office box 1443 ? houston, texas 772511443 cpu description (continued) 'c62x cpu program memory 32-bit address 256-bit data external memory interface data memory 32-bit address 8-, 16-, 32-bit data program fetch instruction dispatch instruction decode data path a register file a data path b register file b .l1 .s1 .m1 .d1 .d2 .m2 .s2 .l2 control registers control logic test emulation interrupts additional peripherals: timers, serial ports, etc. figure 1. 320c62x cpu block diagram

sgus031 april 2000 6 post office box 1443 ? houston, texas 772511443 cpu description (continued) 2x 1x .l2 .s2 .m2 .d2 .d1 .m1 .s1 .l1 long src dst src 2 src 1 src 1 src 1 src 1 src 1 src 1 src 1 src 1 8 8 8 8 8 8 long dst long dst dst dst dst dst dst dst dst src 2 src 2 src 2 src 2 src 2 src 2 src 2 long src da1 da2 st1 ld1 ld2 st2 32 32 register file a (a0a15) long src long dst long dst long src data path b data path a register file b (b0b15) control register file figure 2. 320c62x cpu data paths

sgus031 april 2000 7 post office box 1443 ? houston, texas 772511443 signal groups description hhwil hbe0 hbe1 hcntl0 hcntl1 trst ext_int7 clock/pll jtag emulation reserved data register select half-word/byte select boot mode reset and interrupts little endian big endian dma status power-down status control hpi (host-port interface) 16 control/status tdi tdo tms tck clkin clkout2 clkout1 clkmode1 clkmode0 pllfreq3 pllfreq2 pllfreq1 pllv pllg pllf emu1 emu0 rsv3 rsv2 rsv1 rsv0 hd[15:0] bootmode4 bootmode3 bootmode2 bootmode1 bootmode0 nmi iack inum3 inum2 inum1 inum0 lendian dmac3 dmac2 dmac1 dmac0 pd has hr/w hcs hds1 hds2 hrdy hint rsv7 rsv6 rsv5 rsv4 rsv8 ext_int6 ext_int5 ext_int4 reset rsv9 figure 3. cpu and peripheral signals

sgus031 april 2000 8 post office box 1443 ? houston, texas 772511443 signal groups description (continued) ce3 are ed[31:0] ce2 ce1 ce0 ea[21:2] be3 be2 be1 be0 hold holda tout1 clkx1 fsx1 dx1 clkr1 fsr1 dr1 clks1 aoe awe ardy ssads ssoe sswe ssclk sda10 sdras sdcas sdwe sdclk tout0 clkx0 fsx0 dx0 clkr0 fsr0 dr0 clks0 data memory map space select word address byte enables hold/ holda 32 20 asynchronous memory control sbsram control sdram control emif (external memory interface) timer 1 receive receive timer 0 timers mcbsp1 mcbsp0 transmit transmit clock clock mcbsps (multichannel buffered serial ports) tinp1 tinp0 figure 4. peripheral signals

sgus031 april 2000 9 post office box 1443 ? houston, texas 772511443 signal descriptions signal type 2 description name no. type 2 description clock/pll clkin a14 i clock input clkout1 y6 o clock output at full device speed clkout2 v9 o clock output at half of device speed clkmode1 b17 i clock mode select clkmode0 c17 i ? selects whether the output clock frequency = input clock freq x4 or x1 pllfreq3 c13 pll frequency range (3, 2, and 1) pllfreq2 g11 i ? the target range for clkout1 frequency is determined by the 3-bit value of the pllfreq pins. pllfreq1 f11 i pllv 3 d12 a pll analog v cc connection for the low-pass filter pllg 3 g10 a pll analog gnd connection for the low-pass filter pllf c12 a pll low-pass filter connection to external components and a bypass capacitor jtag emulation tms k19 i jtag test port mode select (features an internal pull-up) tdo r12 o/z jtag test port data out tdi r13 i jtag test port data in (features an internal pull-up) tck m20 i jtag test port clock trst n18 i jtag test port reset (features an internal pull-down) emu1 r20 i/o/z emulation pin 1, pull-up with a dedicated 20-k w resistor emu0 t18 i/o/z emulation pin 0, pull-up with a dedicated 20-k w resistor reset and interrupts reset j20 i device reset nmi k21 i nonmaskable interrupt ? edge-driven (rising edge) ext_int7 r16 ext_int6 p20 i external interrupts ext_int5 r15 i external interru ts ? edge-driven (rising edge) ext_int4 r18 g(gg) iack r11 o interrupt acknowledge for all active interrupts serviced by the cpu inum3 t19 inum2 t20 o active interrupt identification number ? valid during iack for all active interru p ts (not just external) inum1 t14 o ? valid during iack for all active interrupts (not just external) ? en cod in g o r de r f o ll o w s t h e in te rr u p t se rvi ce f etc h p ac k et o r de rin g inum0 t16 ? encoding order follows the interru t service fetch acket ordering little endian/big endian lendian g20 i if high, selects little-endian byte/half-word addressing order within a word if low, selects big-endian addressing power down status pd d19 o power-down mode 2 or 3 (active if high) 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground 3 pllv and pllg signals are not part of external voltage supply or ground. see the clock/pll documentation for information on how to connect those pins. a = analog signal (pll filter)

sgus031 april 2000 10 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description host port interface (hpi) hint h2 o/z host interrupt (from dsp to host) hcntl1 j6 i host control selects between control, address or data registers hcntl0 h6 i host control selects between control, address or data registers hhwil e4 i host halfword select first or second halfword (not necessarily high or low order) hbe1 g6 i host byte select within word or half-word hbe0 f6 i host byte select within word or half-word hr/w d4 i host read or write select hd15 d11 hd14 b11 hd13 a11 hd12 g9 hd11 d10 hd10 a10 hd9 c10 hd8 b9 i/o/z host port data (used for transfer of data address and control) hd7 f9 i/o/z host port data (used for transfer of data, address and control) hd6 c9 hd5 a9 hd4 b8 hd3 d9 hd2 d8 hd1 b7 hd0 c7 has l6 i host address strobe hcs c5 i host chip select hds1 c4 i host data strobe 1 hds2 k6 i host data strobe 2 hrdy h3 o host ready (from dsp to host) boot mode bootmode4 b16 bootmode3 g14 bootmode2 f15 i boot mode bootmode1 c18 i boot mode bootmode0 d17 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 11 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description emif control signals common to all types of memory ce3 y5 o/z ce2 v3 o/z memory space enables ce1 t6 o/z ? enabled by bits 24 and 25 of the word address ce0 u2 o/z ? only one asserted during any external data access be3 r8 o/z byte enable control be2 t3 o/z ? decoded from the two lowest bits of the internal address be1 t2 o/z ? byte write enables for most types of memory be0 r2 o/z ? can be directly connected to sdram read and write mask signal (sdqm) emif address ea21 l4 ea20 l3 ea19 j2 ea18 j1 ea17 k1 ea16 k2 ea15 l2 ea14 l1 ea13 m1 ea12 m2 o/z external address (word address) ea11 m6 o/z external address (word address) ea10 n4 ea9 n1 ea8 n2 ea7 n6 ea6 p4 ea5 p3 ea4 p2 ea3 p1 ea2 p6 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 12 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description emif data ed31 u18 ed30 u20 ed29 t15 ed28 v18 ed27 v17 ed26 v16 ed25 t12 ed24 w17 ed23 t13 ed22 y17 ed21 t11 ed20 y16 ed19 w15 ed18 v14 ed17 y15 ed16 r9 i/o/z external data ed15 y14 i/o/z external data ed14 v13 ed13 aa13 ed12 t10 ed11 y13 ed10 w12 ed9 y12 ed8 y11 ed7 v10 ed6 aa10 ed5 y10 ed4 w10 ed3 y9 ed2 aa9 ed1 y8 ed0 w9 emif asynchronous memory control are r7 o/z asynchronous memory read enable aoe t7 o/z asynchronous memory output enable awe v5 o/z asynchronous memory write enable ardy r4 i asynchronous memory ready input 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 13 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description emif synchronous burst sram control ssads v8 o/z sbsram address strobe ssoe w7 o/z sbsram output enable sswe y7 o/z sbsram write enable ssclk aa8 o/z sbsram clock emif synchronous dram control sda10 v7 o/z sdram address 10 (separate for deactivate command) sdras v6 o/z sdram row address strobe sdcas w5 o/z sdram column address strobe sdwe t8 o/z sdram write enable sdclk t9 o/z sdram clock emif bus arbitration hold r6 i hold request from the host holda b15 o hold request acknowledge to the host timers tout1 g2 o/z timer 1 or general-purpose output tinp1 k3 i timer 1 or general-purpose input tout0 m18 o/z timer 0 or general-purpose output tinp0 j18 i timer 0 or general-purpose input dma action complete dmac3 e18 dmac2 f19 o dma action complete dmac1 e20 o dma action complete dmac0 g16 multichannel buffered serial port 1 (mcbsp1) clks1 f4 i external clock source (as opposed to internal) clkr1 h4 i/o/z receive clock clkx1 j4 i/o/z transmit clock dr1 e2 i receive data dx1 g4 o/z transmit data fsr1 f3 i/o/z receive frame sync fsx1 f2 i/o/z transmit frame sync 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 14 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description multichannel buffered serial port 0 (mcbsp0) clks0 k18 i external clock source (as opposed to internal) clkr0 l21 i/o/z receive clock clkx0 k20 i/o/z transmit clock dr0 j21 i receive data dx0 m21 o/z transmit data fsr0 p16 i/o/z receive frame sync fsx0 n16 i/o/z transmit frame sync reserved for test rsv0 n21 i reserved for testing, pull-up with a dedicated 20-k w resistor rsv1 k16 i reserved for testing, pull-up with a dedicated 20-k w resistor rsv2 b13 i reserved for testing, pull-up with a dedicated 20-k w resistor rsv3 b14 i reserved for testing, pull-up with a dedicated 20-k w resistor rsv4 f13 i reserved for testing, pull-down with a dedicated 20-k w resistor rsv5 c15 o reserved (leave unconnected, do not connect to power or ground) rsv6 f7 i reserved for testing, pull-up with a dedicated 20-k resistor rsv7 d7 i reserved for testing, pull-up with a dedicated 20-k resistor rsv8 b5 i reserved for testing, pull-up with a dedicated 20-k resistor rsv9 f16 o reserved (leave unconnected, do not connect to power or ground) supply voltage pins c14 c8 e19 e3 h11 h13 h9 j10 j12 j14 dv dd j19 s 3.3-v supply voltage dv dd j3 s 3 . 3v su ly voltage j8 k11 k13 k15 k7 k9 l10 l12 l14 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 15 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description supply voltage pins (continued) l8 m11 m13 m15 m7 m9 n10 n12 n14 dv dd n19 s 3.3-v supply voltage dv dd n3 s 3 . 3v su ly voltage n8 p11 p13 p9 u19 u3 w14 w8 a12 a13 b10 b12 b6 d15 d16 f10 f14 cv f8 s 1 8 v supply voltage cv dd g13 s 1.8-v supply voltage g7 g8 k4 m3 m4 a3 a5 a7 a16 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 16 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description supply voltage pins (continued) a18 aa4 aa6 aa15 aa17 aa19 b2 b4 b19 c1 c3 c20 d2 d21 e1 e6 cv e8 s 1 8 v supply voltage cv dd e10 s 1.8-v supply voltage e12 e14 e16 f5 f17 f21 g1 h5 h17 k5 k17 m5 m17 p5 p17 r21 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 17 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description supply voltage pins (continued) t1 t5 t17 u6 u8 u10 u12 u14 u16 u21 v1 v20 w2 w19 w21 y3 y18 y20 cv dd aa11 s 1.8-v supply voltage cv dd aa12 s 1 . 8v su ly voltage f20 g18 h16 h18 l18 l19 l20 n20 p18 p19 r10 r14 u4 v11 v12 v15 w13 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 18 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description ground pins c11 c16 c6 d5 g3 h10 h12 h14 h7 h8 j11 j13 j7 j9 k8 l7 l9 m8 n7 v ss r3 gnd ground pins v ss a4 gnd ground ins a6 a8 a15 a17 a19 aa3 aa5 aa7 aa14 aa16 aa18 b3 b18 b20 c2 c19 c21 d1 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 19 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description ground pins (continued) d20 e5 e7 e9 e11 e13 e15 e17 e21 f1 g5 g17 g21 h1 j5 j17 l5 v ss l17 gnd ground pins v ss n5 gnd ground ins n17 p21 r1 r5 r17 t21 u1 u5 u7 u9 u11 u13 u15 u17 v2 v21 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 20 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description ground pins (continued) w1 w3 w20 y2 y4 y19 f18 g19 h15 j15 j16 k10 k12 k14 l11 l13 l15 v ss m10 gnd ground pins v ss m12 gnd ground ins m14 n11 n13 n15 n9 p10 p12 p14 p15 p7 p8 r19 t4 w11 w16 w6 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 21 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description remaining unconnected pins d13 d14 d18 d3 d6 f12 g12 g15 nc h19 unconnected pins nc h20 unconnected pins h21 l16 m16 m19 v19 v4 w18 w4 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sgus031 april 2000 22 post office box 1443 ? houston, texas 772511443 development support texas instruments offers an extensive line of development tools for the 'c6000 generation of dsps, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of 'c6000-based applications: software development tools: assembly optimizer assembler/linker simulator optimizing ansi c compiler application algorithms c/assembly debugger and code profiler hardware development tools: extended development system (xds ? ) emulator (supports 'c6000 multiprocessor system debug) evm (evaluation module) the tms320 dsp development support reference guide (spru011) contains information about development-support products for all tms320 family member devices, including documentation. see this document for further information on tms320 documentation or any tms320 support products from texas instruments. an additional document, the tms320 third-party support reference guide (spru052), contains information about tms320-related products from other companies in the industry. to receive tms320 literature, contact the product information center at (800) 477-8924. see table 2 for a complete listing of development-support tools for the 'c6000. for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. table 2. 320c6000 development-support tools development tool platform part number software ada 95 compiler 2 sun solaris 2.3 ? 3 ad0345as8500rf - single user ad0345bs8500rf - multi-user c compiler/assembler/linker/assembly optimizer win32 ? tmdx3246855-07 c compiler/assembler/linker/assembly optimizer sparc ? solaris ? tmdx324655-07 simulator win32 tmds3246851-07 simulator sparc solaris tmds3246551-07 xds510 ? debugger/emulation software win32, windows nt ? tmdx324016x-07 hardware xds510 emulator pc tmds00510 xds510ws ? emulator ? scsi tmds00510ws software/hardware evm evaluation kit pc/win95/windows nt tmdx3260a6201 evm evaluation kit (including tmdx324685507) pc/win95/windows nt tmdx326006201 2 contact irvine compiler corporation (949) 250-1366 to order. 3 nt support estimated availability 1q00. includes xds510 board and jtag emulation cable. tmdx324016x-07 c-source debugger/emulation software is not included. ? includes xds510ws box, scsi cable, power supply, and jtag emulation cable. xds, xds510, and xds510ws are trademarks of texas instruments incorporated. win32 and windows nt are trademarks of microsoft corporation. sparc is a trademark of sparc international, inc. solaris is a trademark of sun microsystems, inc.

sgus031 april 2000 23 post office box 1443 ? houston, texas 772511443 device and development-support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all tms320 devices and support tools. each tms320 member has one of three prefixes: smx, sm, or smj. texas instruments recommends two of three possible prefix designators for support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (smx/tmdx) through fully qualified production devices/tools (smj/tmds). this development flow follows. device development evolutionary flow: smx experimental device that is not necessarily representative of the final device's electrical specifications, 25 c tested, military/industrial ceramic dimpled ball grid array package sm fully ti-qualified production device; offered in extended temperature ranges: 40 c to +90 c (s range), and 55 c to +115 c (w range); in ceramic dimpled bga package smj fully smd-qualified production device, 55 c to +115 c (w temperature range), in the ceramic dimpled ball grid array package processed to mil-prf-38535 support tool development evolutionary flow: tmdx development-support product that has not yet completed t exas instruments internal qualification testing. tmds fully qualified development-support product tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: adevelopmental product is intended for internal evaluation purposes.o tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (smx or sm) have a greater failure rate than the standard production devices. t exas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also incl udes a suffix with the device family name. this suffix indicates the package type (glp) and the device speed range in megahertz (for example, 15 is 150 mhz). figure 5 provides a legend for reading the complete device name.

sgus031 april 2000 24 post office box 1443 ? houston, texas 772511443 device and development-support tool nomenclature (continued) prefix device speed range smj 320 c 6201b glp 15 smx = experimental device smj = mil-prf-38535, qml sm = commercial processing device family 320 = tms320 family technology 15 = 150 mhz 16 = 160 mhz 20 = 200 mhz package type 2 glp = 429-ball ceramic bga c = cmos device '6x dsp: 6201 6201b 6203 6701 2 bga = ball grid array w temperature range s = 40 to 90 c, extended temperature w = 55 to 115 c, extended temperature figure 5. tms320 device nomenclature (including smj320c6201b) documentation support extensive documentation supports all tms320 family generations of devices from product announcement through applications development. the types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. the following is a brief, descriptive list of support documentation specific to the 'c6x devices: the tms320c6000 cpu and instruction set reference guide (literature number spru189) describes the 'c6000 cpu architecture, instruction set, pipeline, and associated interrupts. the tms320c6000 peripherals reference guide (literature number spru190) describes the functionality of the peripherals available on 'c6x devices, such as the external memory interface (emif), host-port interface (hpi), multichannel buffered serial ports (mcbsps), direct-memory-access (dma), enhanced direct-memory-access (edma) controller, expansion bus (xb), clocking and phase-locked loop (pll); and power-down modes. this guide also includes information on internal data and program memories. the tms320c6000 programmer's guide (literature number spru198) describes ways to optimize c and assembly code for 'c6x devices and includes application program examples. the tms320c6x c source debugger user's guide (literature number spru188) describes how to invoke the 'c6x simulator and emulator versions of the c source debugger interface and discusses various aspects of the debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis. the tms320c6x peripheral support library programmer's reference (literature number spru273) describes the contents of the 'c6x peripheral support library of functions and macros. it lists functions and macros both by header file and alphabetically, provides a complete description of each, and gives code examples to show how they are used.

sgus031 april 2000 25 post office box 1443 ? houston, texas 772511443 documentation support (continued) tms320c6000 assembly language tools user's guide (literature number spru186) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the 'c6000 generation of devices. the tms320c6x evaluation module reference guide (literature number spru269) provides instructions for installing and operating the 'c6x evaluation module. it also includes support software documentation, application programming interfaces, and technical reference material. tms320c62x multichannel evaluation module user's guide (literature number spru285) provides instructions for installing and operating the 'c62x multichannel evaluation module. it also includes support software documentation, application programming interfaces, and technical reference material. tms320c62x multichannel evaluation module technical reference (spru308) provides provides technical reference information for the 'c62x multichannel evaluation module (mcevm). it includes support software documentation, application programming interface references, and hardware descriptions for the 'c62x mcevm. tms320c6000 dsp/bios user's guide (literature number spru303) describes how to use dsp/bios tools and apis to analyze embedded real-time dsp applications. code composer user's guide (literature number spru296) explains how to use the code composer development environment to build and debug embedded real-time dsp applications. code composer studio t utorial (literature number spru301) introduces the code composer studio integrated development environment and software tools. the tms320c6000 technical brief (literature number spru197) gives an introduction to the 'c62x/c67x devices, associated development tools, and third-party support. a series of dsp textbooks is published by prentice-hall and john wiley & sons to support dsp research and education. the tms320 newsletter, details on signal processing , is published quarterly and distributed to update tms320 customers on product information. the tms320 dsp bulletin board service (bbs) provides access to information pertaining to the tms320 family, including documentation, source code, and object code for many dsp algorithms and utilities. the bbs can be reached at 281/274-2323. information regarding ti dsp products is also available on the worldwide web at http://www.ti.com uniform resource locator (url).

sgus031 april 2000 26 post office box 1443 ? houston, texas 772511443 clock pll all of the 'c62x clocks are generated from a single source through the clkin pin. this source clock either drives the pll, which generates the internal cpu clock, or bypasses the pll to become the cpu clock. to use the pll to generate the cpu clock, the filter circuit shown in figure 6 must be properly designed. for the 'c6201b, it must be powered by the i/o voltage (3.3 v). to configure the 'c62x pll clock for proper operation, see figure 6 and table 3. to minimize the clock jitter, a single clean power supply should power both the 'c62x device and the external clock oscillator circuit. the minimum clkin rise and fall times should also be observed. see the input and output clocks section for input clock timing requirements. clkin pllv pllf pllg 0 1 0 'c6201b clkout1 frequency range 130233 mhz 0 0 1 'c6201b clkout1 frequency range 65200 mhz 0 0 0 'c6201b clkout1 frequency range 50140 mhz pllfreq3 pllfreq2 pllfreq1 clkout 11 01 10 00 mult 4 reserved reserved mult 1 f(clkout)=f(clkin) 4 f(clkout)=f(clkin) 10 m f 0.1 m f (bypass) c1 c2 r1 3.3 v clkmode0 clkmode1 clkout1 clkout2 ssclk sdclk emif 'c6201b 2.5 v gnd 2 1 in 3 out emi filter notes: a. for the ' c6201b clkmode x4, values for c1, c2, and r1 are fixed and apply to all valid frequency ranges of clkin and clkout. b. for clkmode x1, the pll is bypassed and all six external pll components can be removed. for this case, the pllv terminal has to be connected to a clean supply and the pllg and pllf terminals should be tied together. c. due to overlap of frequency ranges when choosing the pllfreq, more than one frequency range can contain the clkout1 frequency. choose the lowest frequency range that includes the desired frequency. for example, for clkout1 = 133 mhz, a pllfreq value of 000b should be used for the 'c6201b. for clkout1 = 200 mhz, pllfreq should be set to 001b for the 'c6201b. pllfreq values other than 000b, 001b, and 010b are reserved. d. for the 'c6201b, the 3.3-v supply for the emi filter (and pllv) must be from the same 3.3-v power plane supplying the i/o vol tage, dv dd . figure 6. pll block diagram

sgus031 april 2000 27 post office box 1443 ? houston, texas 772511443 clock pll (continued) table 3. 320c6201b pll component selection table clkmode clkin range (mhz) cpu clock frequency (clkout1) range (mhz) clkout2 range (mhz) r1 ( w ) c1 (nf) c2 (pf) typical lock time ( m s) 2 x4 12.550 50200 25100 60.4 27 560 75 2 under some operating conditions, the maximum pll lock time may vary as much as 150% from the specified typical value. for examp le, if the typical lock time is specified as 100 m s, the maximum value may be as long as 250 m s. power supply sequencing for the 'c6201b device, the 1.8-v supply powers the core and the 3.3-v supply powers the i/o buffers. the core supply should be powered up first, or at the same time as the i/o buffers. this is to ensure that the i/o buffers have valid inputs from the core before the output buffers are powered up, thus preventing bus contention with other chips on the board.

sgus031 april 2000 28 post office box 1443 ? houston, texas 772511443 absolute maximum ratings over operating case temperature range (unless otherwise noted) 2 supply voltage range, cv dd (see note 1) 0.3 v to 2.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, dv dd (see note 1) 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating case temperature range t c : (s temp version) 40 c to 90 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (w temp version) 55 c to 115 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . recommended operating conditions 'c6201b unit min nom max unit cv dd supply voltage 1.71 1.8 1.89 v dv dd supply voltage 3.14 3.30 3.46 v v ss supply ground 0 0 0 v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i oh high-level output current 12 ma i ol low-level output current 12 ma t o p erating case tem p erature 3 s temp version 40 90 c t c operating case temperature 3 w temp version 55 115 c 3 case temperature is measured at package bottom. there is no direct thermal path from the chip through the lid.

sgus031 april 2000 29 post office box 1443 ? houston, texas 772511443 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) parameter test conditions 'c6201b unit parameter test conditions min typ max unit v oh high-level output voltage dv dd = min, i oh = max 2.4 v v ol low-level output voltage dv dd = min, i ol = max 0.6 v i i input current 2 v i = v ss to dv dd 10 ua i oz off-state output current v o = dv dd or 0 v 10 ua i dd2v supply current, cpu + cpu memory access 3 cv dd = nom, cpu clock = 167 mhz 380 ma i dd2v supply current, peripherals cv dd = nom, cpu clock = 167 mhz 240 ma i dd3v supply current, i/o pins ? dv dd = nom, cpu clock = 167 mhz 90 ma c i input capacitance 15 pf c o output capacitance 15 pf 2 tms and tdi are not included due to internal pullups. trst is not included due to internal pulldown. 3 measured with average cpu activity: 50% of time: 8 instructions per cycle, 32-bit dmem access per cycle 50% of time: 2 instructions per cycle, 16-bit dmem access per cycle measured with average peripheral activity: 50% of time: timers at max rate, mcbsps at e1 rate, and dma burst transfer between dmem and sdram 50% of time: timers at max rate, mcbsps at e1 rate, and dma servicing mcbsps ? measured with average i/o activity (30-pf load): 25% of time: reads from external sdram 25% of time: writes to external sdram 50% of time: no activity

sgus031 april 2000 30 post office box 1443 ? houston, texas 772511443 parameter measurement information tester pin electronics v ref i ol c t = 30 pf 2 i oh output under test 50 w 2 typical distributed load circuit capacitance figure 7. ttl-level outputs signal transition levels all input and output timing parameters are referenced to 1.5 v for both a0o and a1o logic levels. v ref = 1.5 v figure 8. input and output voltage reference levels for ac timing measurements

sgus031 april 2000 31 post office box 1443 ? houston, texas 772511443 input and output clocks timing requirements for clkin (see figure 9) 'c6201b-15 'c6201b-20 no. clkmode = x4 clkmode = x1 clkmode = x4 clkmode = x1 unit min max min max min max min max 1 t c(clkin) cycle time, clkin 26.7 6.67 20 5 ns 2 t w(clkinh) pulse duration, clkin high *9.8 *2.7 *8 *2.35 ns 3 t w(clkinl) pulse duration, clkin low *9.8 *2.7 *8 *2.35 ns 4 t t(clkin) transition time, clkin *5 *0.6 *5 *0.6 ns *not production tested. clkin 1 2 3 4 4 figure 9. clkin timings switching characteristics for clkout1 23 (see figure 10) 'c6201b no. parameter clkmode = x4 clkmode = x1 unit no. parameter min max min max unit 1 t c(cko1) cycle time, clkout1 *p 0.7 *p + 0.7 *p 0.7 *p + 0.7 ns 2 t w(cko1h) pulse duration, clkout1 high *(p/2) 0.5 *(p/2 ) + 0.5 *ph 0.5 *ph + 0.5 ns 3 t w(cko1l) pulse duration, clkout1 low *(p/2) 0.5 *(p/2 ) + 0.5 *pl 0.5 *pl + 0.5 ns 4 t t(cko1) transition time, clkout1 *0.6 *0.6 ns 2 ph is the high period of clkin in ns and pl is the low period of clkin in ns. 3 p = 1/cpu clock frequency in nanoseconds (ns). *not production tested. clkout1 1 3 4 4 2 figure 10. clkout1 timings #& ')%+#'& '&)&* ()',+* #& +" ')%+#- ') *#!& ("* ' -$'(%&+ ")+)#*+# + & '+") *(# #+#'&* ) *#!& !'$* /* &*+),%&+* )*)-* +" )#!"+ +' "&! ') #*'&+#&, +"* ()',+* .#+"',+ &'+#

sgus031 april 2000 32 post office box 1443 ? houston, texas 772511443 input and output clocks (continued) switching characteristics for clkout2 2 (see figure 11) no parameter 'c6201b unit no. parameter min max unit 1 t c(cko2) cycle time, clkout2 *2p 0.7 *2p + 0.7 ns 2 t w(cko2h) pulse duration, clkout2 high *p 0.9 *p + 0.7 ns 3 t w(cko2l) pulse duration, clkout2 low *p 0.7 *p + 0.9 ns 4 t t(cko2) transition time, clkout2 *0.6 ns 2 p = 1/cpu clock frequency in ns. *not production tested. clkout2 1 2 3 4 4 figure 11. clkout2 timings

sgus031 april 2000 33 post office box 1443 ? houston, texas 772511443 input and output clocks (continued) sdclk, ssclk timing parameters sdclk timing parameters are the same as clkout2 parameters. ssclk timing parameters are the same as clkout1 or clkout2 parameters, depending on ssclk configuration. switching characteristics for the relation of ssclk, sdclk, and clkout2 to clkout1 (see figure 12) 2 no parameter 'c6201b unit no. parameter min max unit 1 t d(cko1-ssclk) delay time, clkout1 edge to ssclk edge (p/2) + 0.2 (p/2) + 4.2 ns 2 t d(cko1-ssclk1/2) delay time, clkout1 edge to ssclk edge (1/2 clock rate) (p/2) 1 (p/2) + 2.4 ns 3 t d(cko1-cko2) delay time, clkout1 edge to clkout2 edge *(p/2) 1 *(p/2) + 2.4 ns 4 t d(cko1-sdclk) delay time, clkout1 edge to sdclk edge (p/2) 1 (p/2) + 2.4 ns 2 p = 1/cpu clock frequency in ns. *not production tested. 4 3 2 1 clkout1 ssclk ssclk (1/2rate) clkout2 sdclk figure 12. relation of clkout2, sdclk, and ssclk to clkout1

sgus031 april 2000 34 post office box 1443 ? houston, texas 772511443 asynchronous memory timing timing requirements for asynchronous memory cycles 2 (see figure 13 and figure 14) no 'c6201b unit no. min max unit 6 t su(edv-cko1h) setup time, read edx valid before clkout1 high 4.0 ns 7 t h(cko1h-edv) hold time, read edx valid after clkout1 high 0.8 ns 10 t su(ardy-cko1h) setup time, ardy valid before clkout1 high 3.0 ns 11 t h(cko1h-ardy) hold time, ardy valid after clkout1 high 1.8 ns 2 to ensure data setup time, simply program the strobe width wide enough. ardy is internally synchronized. if ardy does meet setu p or hold time, it may be recognized in the current cycle or the next cycle. thus, ardy can be an asynchronous input. switching characteristics for asynchronous memory cycles 3 (see figure 13 and figure 14) no parameter 'c6201b unit no. parameter min max unit 1 t d(cko1h-cev) delay time, clkout1 high to cex valid 0.2 4.0 ns 2 t d(cko1h-bev) delay time, clkout1 high to bex valid 4.0 ns 3 t d(cko1h-beiv) delay time, clkout1 high to bex invalid *0.2 ns 4 t d(cko1h-eav) delay time, clkout1 high to eax valid 4.0 ns 5 t d(cko1h-eaiv) delay time, clkout1 high to eax invalid *0.2 ns 8 t d(cko1h-aoev) delay time, clkout1 high to aoe valid 0.2 4.0 ns 9 t d(cko1h-arev) delay time, clkout1 high to are valid 0.2 4.0 ns 12 t d(cko1h-edv) delay time, clkout1 high to edx valid 4.0 ns 13 t d(cko1h-ediv) delay time, clkout1 high to edx invalid *0.2 ns 14 t d(cko1h-awev) delay time, clkout1 high to awe valid 0.2 4.0 ns 3 the minimum delay is also the minimum output hold after clkout1 high. *not production tested.

sgus031 april 2000 35 post office box 1443 ? houston, texas 772511443 asynchronous memory timing (continued) 11 11 10 10 9 9 8 8 7 6 5 4 3 2 1 1 clkout1 cex be[3:0] ea[21:2] ed[31:0] aoe are awe ardy setup = 2 strobe = 5 not ready = 2 hold = 1 figure 13. asynchronous memory read timing 11 10 11 10 14 14 13 12 5 4 3 2 1 1 clkout1 cex be[3:0] ea[21:2] ed[31:0] aoe are awe ardy setup = 2 strobe = 5 not ready = 2 hold = 1 figure 14. asynchronous memory write timing

sgus031 april 2000 36 post office box 1443 ? houston, texas 772511443 synchronous-burst memory timing timing requirements for synchronous-burst sram cycles (full-rate ssclk) (see figure 15) no 'c6201b unit no. min max unit 7 t su(edv-ssclkh) setup time, read edx valid before ssclk high 1.7 ns 8 t h(ssclkh-edv) hold time, read edx valid after ssclk high 1.5 ns switching characteristics for synchronous-burst sram cycles 2 (full-rate ssclk) (see figure 15 and figure 16) no parameter 'c6201b unit no. parameter min max unit 1 t osu(cev-ssclkh) output setup time, cex valid before ssclk high 0.5p 1.3 ns 2 t oh(ssclkh-cev) output hold time, cex valid after ssclk high 0.5p 2.3 ns 3 t osu(bev-ssclkh) output setup time, bex valid before ssclk high 0.5p 1.3 ns 4 t oh(ssclkh-beiv) output hold time, bex invalid after ssclk high *0.5p 2.3 ns 5 t osu(eav-ssclkh) output setup time, eax valid before ssclk high 0.5p 1.3 ns 6 t oh(ssclkh-eaiv) output hold time, eax invalid after ssclk high *0.5p 2.3 ns 9 t osu(adsv-ssclkh) output setup time, ssads valid before ssclk high 0.5p 1.3 ns 10 t oh(ssclkh-adsv) output hold time, ssads valid after ssclk high 0.5p 2.3 ns 11 t osu(oev-ssclkh) output setup time, ssoe valid before ssclk high 0.5p 1.3 ns 12 t oh(ssclkh-oev) output hold time, ssoe valid after ssclk high 0.5p 2.3 ns 13 t osu(edv-ssclkh) output setup time, edx valid before ssclk high 0.5p 1.3 ns 14 t oh(ssclkh-ediv) output hold time, edx invalid after ssclk high *0.5p 2.3 ns 15 t osu(wev-ssclkh) output setup time, sswe valid before ssclk high 0.5p 1.3 ns 16 t oh(ssclkh-wev) output hold time, sswe valid after ssclk high 0.5p 2.3 ns 2 when the pll is used (clkmode x4), p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. for clkmode x1, 0.5p is defined as ph (pulse duration of clkin high) for all output setup times; 0.5p is defined as pl (pulse d uration of clkin low) for all output hold times. *not production tested.

sgus031 april 2000 37 post office box 1443 ? houston, texas 772511443 synchronous-burst memory timing (continued) be1 be2 be3 be4 a1 a2 a3 a4 q1 q2 q3 q4 12 11 10 9 8 7 6 5 4 3 2 1 ssclk cex be[3:0] ea[21:2] ed[31:0] ssads ssoe sswe figure 15. sbsram read timing (full-rate ssclk) be1 be2 be3 be4 a1 a2 a3 a4 d1 d2 d3 d4 16 15 10 9 14 13 6 5 4 3 2 1 ssclk cex be[3:0] ea[21:2] ed[31:0] ssads ssoe sswe figure 16. sbsram write timing (full-rate ssclk)

sgus031 april 2000 38 post office box 1443 ? houston, texas 772511443 synchronous-burst memory timing (continued) timing requirements for synchronous-burst sram cycles (half-rate ssclk) (see figure 17) no 'c6201b unit no. min max unit 7 t su(edv-ssclkh) setup time, read edx valid before ssclk high 2.5 ns 8 t h(ssclkh-edv) hold time, read edx valid after ssclk high 1.5 ns switching characteristics for synchronous-burst sram cycles 2 (half-rate ssclk) (see figure 17 and figure 18) no parameter 'c6201b unit no. parameter min max unit 1 t osu(cev-ssclkh) output setup time, cex valid before ssclk high 1.5p 3 ns 2 t oh(ssclkh-cev) output hold time, cex valid after ssclk high 0.5p 1.5 ns 3 t osu(bev-ssclkh) output setup time, bex valid before ssclk high 1.5p 3 ns 4 t oh(ssclkh-beiv) output hold time, bex invalid after ssclk high *0.5p 1.5 ns 5 t osu(eav-ssclkh) output setup time, eax valid before ssclk high 1.5p 3 ns 6 t oh(ssclkh-eaiv) output hold time, eax invalid after ssclk high *0.5p 1.5 ns 9 t osu(adsv-ssclkh) output setup time, ssads valid before ssclk high 1.5p 3 ns 10 t oh(ssclkh-adsv) output hold time, ssads valid after ssclk high 0.5p 1.5 ns 11 t osu(oev-ssclkh) output setup time, ssoe valid before ssclk high 1.5p 3 ns 12 t oh(ssclkh-oev) output hold time, ssoe valid after ssclk high 0.5p 1.5 ns 13 t osu(edv-ssclkh) output setup time, edx valid before ssclk high 1.5p 3 ns 14 t oh(ssclkh-ediv) output hold time, edx invalid after ssclk high *0.5p 1.5 ns 15 t osu(wev-ssclkh) output setup time, sswe valid before ssclk high 1.5p 3 ns 16 t oh(ssclkh-wev) output hold time, sswe valid after ssclk high 0.5p 1.5 ns 2 when the pll is used (clkmode x4), p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. for clkmode x1: 1.5p = p + ph, where p = 1/cpu clock frequency, and ph = pulse duration of clkin high. 0.5p = pl, where pl = pulse duration of clkin low. *not production tested. #& ')%+#'& '&)&* ()',+* #& +" ')%+#- ') *#!& ("* ' -$'(%&+ ")+)#*+# + & '+") *(# #+#'&* ) *#!& !'$* /* &*+),%&+* )*)-* +" )#!"+ +' "&! ') #*'&+#&, +"* ()',+* .#+"',+ &'+#

sgus031 april 2000 39 post office box 1443 ? houston, texas 772511443 synchronous-burst memory timing (continued) ssclk cex be[3:0] ea[21:2] ed[31:0] ssads ssoe sswe be1 be2 be3 be4 a1 a2 a3 a4 q1 q2 q3 q4 12 11 10 9 6 5 4 3 2 1 8 7 figure 17. sbsram read timing (1/2 rate ssclk) ssclk cex be[3:0] ea[21:2] ed[31:0] ssoe sswe ssads be1 be2 be3 be4 a1 a2 a3 a4 q1 q2 q3 q4 16 15 10 9 14 13 6 5 4 3 2 1 figure 18. sbsram write timing (1/2 rate ssclk)

sgus031 april 2000 40 post office box 1443 ? houston, texas 772511443 synchronous dram timing timing requirements for synchronous dram cycles (see figure 19) no 'c6201b unit no. min max unit 7 t su(edv-sdclkh) setup time, read edx valid before sdclk high 0.5 ns 8 t h(sdclkh-edv) hold time, read edx valid after sdclk high 3 ns switching characteristics for synchronous dram cycles 2 (see figure 19figure 24) no parameter 'c6201b unit no. parameter min max unit 1 t osu(cev-sdclkh) output setup time, cex valid before sdclk high 1.5p 3.5 ns 2 t oh(sdclkh-cev) output hold time, cex valid after sdclk high 0.5p 1 ns 3 t osu(bev-sdclkh) output setup time, bex valid before sdclk high 1.5p 3.5 ns 4 t oh(sdclkh-beiv) output hold time, bex invalid after sdclk high *0.5p 1 ns 5 t osu(eav-sdclkh) output setup time, eax valid before sdclk high 1.5p 3.5 ns 6 t oh(sdclkh-eaiv) output hold time, eax invalid after sdclk high *0.5p 1 ns 9 t osu(sdcas-sdclkh) output setup time, sdcas valid before sdclk high 1.5p 3.5 ns 10 t oh(sdclkh-sdcas) output hold time, sdcas valid after sdclk high 0.5p 1 ns 11 t osu(edv-sdclkh) output setup time, edx valid before sdclk high 1.5p 3.5 ns 12 t oh(sdclkh-ediv) output hold time, edx invalid after sdclk high *0.5p 1 ns 13 t osu(sdwe-sdclkh) output setup time, sdwe valid before sdclk high 1.5p 3.5 ns 14 t oh(sdclkh-sdwe) output hold time, sdwe valid after sdclk high 0.5p 1 ns 15 t osu(sda10v-sdclkh) output setup time, sda10 valid before sdclk high 1.5p 3.5 ns 16 t oh(sdclkh-sda10iv) output hold time, sda10 invalid after sdclk high *0.5p 1 ns 17 t osu(sdras-sdclkh) output setup time, sdras valid before sdclk high 1.5p 3.5 ns 18 t oh(sdclkh-sdras) output hold time, sdras valid after sdclk high 0.5p 1 ns 2 when the pll is used (clkmode x4), p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. for clkmode x1: 1.5p = p + ph, where p = 1/cpu clock frequency, and ph = pulse duration of clkin high. 0.5p = pl, where pl = pulse duration of clkin low. *not production tested. #& ')%+#'& '&)&* ()',+* #& +" ')%+#- ') *#!& ("* ' -$'(%&+ ")+)#*+# + & '+") *(# #+#'&* ) *#!& !'$* /* &*+),%&+* )*)-* +" )#!"+ +' "&! ') #*'&+#&, +"* ()',+* .#+"',+ &'+#

sgus031 april 2000 41 post office box 1443 ? houston, texas 772511443 synchronous dram timing (continued) sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe be1 be2 be3 ca1 ca2 ca3 d1 d2 d3 10 9 16 15 6 5 4 3 2 1 8 7 read read read figure 19. three sdram read commands sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe be1 be2 be3 ca1 ca2 ca3 d1 d2 d3 14 13 10 9 16 15 12 11 6 5 4 3 2 1 write write write figure 20. three sdram wrt commands

sgus031 april 2000 42 post office box 1443 ? houston, texas 772511443 synchronous dram timing (continued) sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe bank activate/row address row address 18 17 15 5 2 1 actv figure 21. sdram actv command sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe 14 18 16 2 15 1 17 13 dcab figure 22. sdram dcab command

sgus031 april 2000 43 post office box 1443 ? houston, texas 772511443 synchronous dram timing (continued) sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe 10 9 18 17 2 1 refr figure 23. sdram refr command sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe mrs value 14 10 18 6 2 1 5 17 9 13 mrs figure 24. sdram mrs command

sgus031 april 2000 44 post office box 1443 ? houston, texas 772511443 hold /holda timing timing requirements for the hold /holda cycles 2 (see figure 25) no 'c6201b unit no. min max unit 1 t su(holdh-cko1h) setup time, hold high before clkout1 high *1 ns 2 t h(cko1h-holdl) hold time, hold low after clkout1 high *4 ns 2 hold is synchronized internally. therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. thus, hold can be an asynchronous input. *not production tested. switching characteristics for the hold /holda cycles 3 (see figure 25) no parameter 'c6201b unit no. parameter min max unit 3 t r(holdl-bhz) response time, hold low to emif bus high impedance *4p ns 4 t r(bhz-holdal) response time, emif bus high impedance to holda low *p *2p ns 5 t r(holdh-holdah) response time, hold high to holda high *4p *7p ns 6 t d(cko1h-holdal) delay time, clkout1 high to holda valid *1 8 ns 7 t d(cko1h-bhz) delay time, clkout1 high to emif bus high impedance ? *3 *11 ns 8 t d(cko1h-blz) delay time, clkout1 high to emif bus low impedance ? *3 *11 ns 9 t r(holdh-blz) response time, hold high to emif bus low impedance *3p *6p ns 3 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. *not production tested. all pending emif transactions are allowed to complete before holda is asserted. the worst cases for this is an asynchronous read or write with external ardy used or a minimum of eight consecutive sdram reads or writes when rbtr8 = 1. if no bus transactions are occurring , then the minimum delay time can be achieved. also, bus hold can be indefinitely delayed by setting nohold = 1. ? emif bus consists of ce[3:0] , be[3:0] , ed[31:0], ea[21:2], are , aoe , awe , ssads , ssoe , sswe , sda10, sdras , sdcas , and sdwe . dsp owns bus external requester dsp owns bus 'c62x ext req 'c62x 8 7 3 4 6 6 1 2 clkout1 hold holda emif bus 2 1 5 9 2 2 emif bus consists of ce[3:0] , be[3:0] , ed[31:0], ea[21:2], are , aoe , awe , ssads , ssoe , sswe , sda10, sdras , sdcas , and sdwe . figure 25. hold /holda timing

sgus031 april 2000 45 post office box 1443 ? houston, texas 772511443 reset timing timing requirements for reset (see figure 26) no 'c6201b unit no. min max unit 1 t w(rst) width of the reset pulse (pll stable) 2 *10 clkout1 cycles 1 t w (rst) width of the reset pulse (pll needs to sync up) 3 250 m s 2 this parameter applies to clkmode x1 when clkin is stable and applies to clkmode x4 when clkin and pll are stable. 3 this parameter only applies to clkmode x4. the reset signal is not connected internally to the clock pll circuit. the pll, however, may need up to 250 m s to stabilize following device power up or after pll configuration has been changed. during that time, reset must be asserted to ensure proper device operation. see the clock pll section for pll lock times. *not production tested. switching characteristics during reset ? (see figure 26) no parameter 'c6201b unit no. parameter min max unit 2 t r(rst) response time to change of value in reset signal 2 clkout1 cycles 3 t d(cko1h-cko2iv) delay time, clkout1 high to clkout2 invalid *1 ns 4 t d(cko1h-cko2v) delay time, clkout1 high to clkout2 valid 10 ns 5 t d(cko1h-sdclkiv) delay time, clkout1 high to sdclk invalid *1 ns 6 t d(cko1h-sdclkv) delay time, clkout1 high to sdclk valid 10 ns 7 t d(cko1h-ssckiv) delay time, clkout1 high to ssclk invalid *1 ns 8 t d(cko1h-ssckv) delay time, clkout1 high to ssclk valid 10 ns 9 t d(cko1h-lowiv) delay time, clkout1 high to low group invalid *1 ns 10 t d(cko1h-lowv) delay time, clkout1 high to low group valid *10 ns 11 t d(cko1h-highiv) delay time, clkout1 high to high group invalid *1 ns 12 t d(cko1h-highv) delay time, clkout1 high to high group valid *10 ns 13 t d(cko1h-zhz) delay time, clkout1 high to z group high impedance *1 ns 14 t d(cko1h-zv) delay time, clkout1 high to z group valid *10 ns low group consists of: iack, inum[3:0], dmac[3:0], pd, tout0, and tout1 high group consists of: hint z group consists of: ea[21:2], ed[31:0], ce[3:0] , be[3:0] , are , awe , aoe , ssads , ssoe , sswe , sda10, sdras , sdcas , sdwe , hd[15:0], clkx0, clkx1, fsx0, fsx1, dx0, dx1, clkr0, clkr1, fsr0, and fsr1. ? hrdy is gated by input hcs . if hcs = 0 at device reset, hrdy belongs to the high group. if hcs = 1 at device reset, hrdy belongs to the low group. *not production tested.

sgus031 april 2000 46 post office box 1443 ? houston, texas 772511443 reset timing (continued) 1 2 2 14 13 12 11 10 9 8 7 6 5 4 3 clkout1 reset clkout2 sdclk ssclk low group 23 high group 23 z group 23 2 low group consists of: iack, inum[3:0], dmac[3:0], pd, tout0, and tout1 high group consists of: hint z group consists of: ea[21:2], ed[31:0], ce[3:0] , be[3:0] , are , awe , aoe , ssads , ssoe , sswe , sda10, sdras , sdcas , sdwe , hd[15:0], clkx0, clkx1, fsx0, fsx1, dx0, dx1, clkr0, clkr1, fsr0, and fsr1. 3 hrdy is gated by input hcs . if hcs = 0 at device reset, hrdy belongs to the high group. if hcs = 1 at device reset, hrdy belongs to the low group. figure 26. reset timing

sgus031 april 2000 47 post office box 1443 ? houston, texas 772511443 external interrupt timing timing requirements for interrupt response cycles 23 (see figure 27) no 'c6201b unit no. min max unit 2 t w(ilow) width of the interrupt pulse low *2p ns 3 t w(ihigh) width of the interrupt pulse high *2p ns 2 interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violat ed. thus, they can be connected to asynchronous inputs. 3 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. *not production tested. switching characteristics during interrupt response cycles (see figure 27) no parameter 'c6201b unit no. parameter min max unit 1 t r(einth-iackh) response time, ext_intx high to iack high *9p ns 4 t d(cko2l-iackv) delay time, clkout2 low to iack valid *4 6 ns 5 t d(cko2l-inumv) delay time, clkout2 low to inumx valid 6 ns 6 t d(cko2l-inumiv) delay time, clkout2 low to inumx invalid *4 ns p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. when the pll is used (clkmode x4), 0.5p = 1/(2 cpu clock frequency). for clkmode x1: 0.5p = ph, where ph is the high period of clkin. *not production tested. interrupt number 6 5 4 4 3 2 clkout2 ext_intx, nmi 1 intr flag iack inumx figure 27. interrupt timing

sgus031 april 2000 48 post office box 1443 ? houston, texas 772511443 host-port interface timing timing requirements for host-port interface cycles 23 (see figure 28, figure 29, figure 30, and figure 31) no 'c6201b unit no. min max unit 1 t su(sel-hstbl) setup time, select signals valid before hstrobe low 4 ns 2 t h(hstbl-sel) hold time, select signals valid after hstrobe low 2 ns 3 t w(hstbl) pulse duration, hstrobe low 2p ns 4 t w(hstbh) pulse duration, hstrobe high between consecutive accesses *2p ns 10 t su(sel-hasl) setup time, select signals valid before has low 4 ns 11 t h(hasl-sel) hold time, select signals valid after has low 2 ns 12 t su(hdv-hstbh) setup time, host data valid before hstrobe high 4 ns 13 t h(hstbh-hdv) hold time, host data valid after hstrobe high 2 ns 14 t h(hrdyl-hstbl) hold time, hstrobe low after hrdy low. hstrobe shoul not be inactivated until hrdy is active (low); otherwise, hpi writes will not complete properly. *1 ns 18 t su(hasl-hstbl) setup time, has low before hstrobe low *2 ns 19 t h(hstbl-hasl) hold time, has low after hstrobe low *2 ns 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . 3 the effects of internal clock jitter are included at test. there is no need to adjust timing numbers for internal clock jitter. p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. select signals include: hcntrl[1:0], hr/w , and hhwil. *not production tested. switching characteristics during host-port interface cycles 23 (see figure 28, figure 29, figure 30, and figure 31) no parameter 'c6201b unit no. parameter min max unit 5 t d(hcs-hrdy) delay time, hcs to hrdy ? *1 9 ns 6 t d(hstbl-hrdyh) delay time, hstrobe low to hrdy high # *3 12 ns 7 t oh(hstbl-hdlz) output hold time, hd low impedance after hstrobe low for an hpi read *4 ns 8 t d(hdv-hrdyl) delay time, hd valid to hrdy low *p 3 *p + 3 ns 9 t oh(hstbh-hdv) output hold time, hd valid after hstrobe high *1 *12 ns 15 t d(hstbh-hdhz) delay time, hstrobe high to hd high impedance *3 *12 ns 16 t d(hstbl-hdv) delay time, hstrobe low to hd valid *2 *12 ns 17 t d(hstbh-hrdyh) delay time, hstrobe high to hrdy high || *3 12 ns 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . 3 the effects of internal clock jitter are included at test. there is no need to adjust timing numbers for internal clock jitter. p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? hcs enables hrdy , and hrdy is always low when hcs is high. the case where hrdy goes high when hcs falls indicates that hpi is busy completing a previous hpid write or read with autoincrement. # this parameter is used during an hpid read. at the beginning of the first half-word transfer on the falling edge of hstrobe , the hpi sends the request to the dma auxiliary channel, and hrdy remains high until the dma auxiliary channel loads the requested data into hpid. || this parameter is used after the second half-word of an hpid write or autoincrement read. hrdy remains low if the access is not an hpid write or autoincrement read. reading or writing to hpic or hpia does not affect the hrdy signal. *not production tested.

sgus031 april 2000 49 post office box 1443 ? houston, texas 772511443 host-port interface timing (continued) 1st half-word 2nd half-word 5 17 8 6 5 17 8 5 15 9 16 15 9 7 4 3 2 1 2 1 2 1 2 1 2 1 2 1 has hcntl[1:0] hr/w hhwil hstrobe 2 hcs hd[15:0] (output) hrdy (case 1) hrdy (case 2) 3 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 28. hpi read timing (has not used, tied high) has hcntl[1:0] hr/w hhwil hstrobe 2 hcs hd[15:0] (output) hrdy (case 1) hrdy (case 2) 1st half-word 2nd half-word 5 17 8 6 5 17 8 5 15 9 16 15 9 7 4 3 11 10 11 10 11 10 11 10 11 10 11 10 19 19 18 18 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 29. hpi read timing (has used)

sgus031 april 2000 50 post office box 1443 ? houston, texas 772511443 host-port interface timing (continued) 1st half-word 2nd half-word 5 17 5 13 12 13 12 4 14 3 2 1 2 1 2 1 2 1 13 12 13 12 2 1 2 1 has hcntl[1:0] hr/w hhwil hstrobe 2 hcs hd[15:0] (input) hrdy hbe[1:0] 3 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 30. hpi write timing (has not used, tied high) 1st half-word 2nd half-word 5 17 5 13 12 13 12 4 14 3 11 10 11 10 11 10 11 10 11 10 11 10 13 12 13 12 has hcntl[1:0] hr/w hhwil hstrobe 2 hcs hd[15:0] (input) hrdy hbe[1:0] 19 19 18 18 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 31. hpi write timing (has used)y

sgus031 april 2000 51 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing timing requirements for mcbsp 23 (see figure 32) no 'c6201b unit no. min max unit 2 t c(ckrx) cycle time, clkr/x clkr/x ext *2p ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext *p 1 ns 5 t setup time external fsr high before clkr low clkr int *9 ns 5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr ext 2 ns 6 t hold time external fsr high after clkr low clkr int *6 ns 6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr ext 3 ns 7 t setup time dr valid before clkr low clkr int 8 ns 7 t su(drv-ckrl) setup time, dr valid before clkr low clkr ext 1 ns 8 t hold time dr valid after clkr low clkr int 3 ns 8 t h(ckrl-drv) hold time, dr valid after clkr low clkr ext 4 ns 10 t setup time external fsx high before clkx low clkx int 9 ns 10 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx ext 2 ns 11 t hold time external fsx high after clkx low clkx int 6 ns 11 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx ext 3 ns 2 clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are a lso inverted. 3 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. *not production tested

sgus031 april 2000 52 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) switching characteristics for mcbsp 23 (see figure 32) no parameter 'c6201b unit no. parameter min max unit 1 t d(cksh-ckrxh) delay time, clks high to clkr/x high for internal clkr/x generated from clks input 3 10 ns 2 t c(ckrx) cycle time, clkr/x clkr/x int 2p ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x int *c 1.6 ? *c + 1 ? ns 4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int *2.5 3 ns 9 t delay time clkx high to internal fsx valid clkx int *2 3 ns 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx ext *3 *9 ns 12 t disable time, dx hi g h impedance followin g last data bit from clkx int *1 *4 ns 12 t dis(ckxh-dxhz) disable time , dx high im edance following last data bit from clkx high clkx ext *3 *9 ns 13 t delay time clkx high to dx valid clkx int *1 *4 ns 13 t d(ckxh-dxv) delay time, clkx high to dx valid clkx ext *3 *9 ns 14 t delay time, fsx high to dx valid fsx int *1 *3 ns 14 t d(fxh-dxv) only applies when in data delay 0 (xdatdly = 00b) mode fsx ext *3 *9 ns 2 clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are a lso inverted. 3 minimum delay times also represent minimum output hold times. p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. *not production tested. ? c = h or l s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero

sgus031 april 2000 53 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) bit(n-1) (n-2) (n-3) bit 0 bit(n-1) (n-2) (n-3) 14 13 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 clks clkr fsr (int) fsr (ext) dr clkx fsx (int) fsx (ext) fsx (xdatdly=00b) dx 13 figure 32. mcbsp timings

sgus031 april 2000 54 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) timing requirements for fsr when gsync = 1 (see figure 33) no 'c6201b unit no. min max unit 1 t su(frh-cksh) setup time, fsr high before clks high 4 ns 2 t h(cksh-frh) hold time, fsr high after clks high 4 ns 2 1 clks fsr external clkr/x (no need to resync) clkr/x (needs resync) figure 33. fsr timing when gsync = 1 timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 23 (see figure 34) 'c6201b no. master slave unit no. min max min max unit 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 3p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 6p ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1.

sgus031 april 2000 55 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) switching characteristics for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 23 (see figure 34) 'c6201b no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? t 2 *t + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # *l 2 l + 3 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid *2 4 *3p + 4 5p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low *l 2 *l + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high *p + 3 *3p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid *2p + 2 4p + 17 ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp *not production tested. # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 34. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).

sgus031 april 2000 56 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 23 (see figure 35) 'c6201b no. master slave unit no. min max min max unit 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 23 (see figure 35) 'c6201b no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? l 2 *l + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # *t 2 t + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid *2 4 *3p + 4 5p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low *2 *4 *3p + 3 *5p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid *h 2 h + 4 *2p + 2 4p + 17 ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp *not production tested. # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 clkx fsx dx dr 5 figure 35. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0

sgus031 april 2000 57 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 23 (see figure 36) 'c6201b no. master slave unit no. min max min max unit 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 23 (see figure 36) 'c6201b no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? t 2 *t + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # *h 2 h + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid *2 4 *3p + 4 5p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high *h 2 *h + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high *p + 3 *3p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid *2p + 2 4p + 17 ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp *not production tested. # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 36. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1

sgus031 april 2000 58 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 23 (see figure 37) 'c6201b no. master slave unit no. min max min max unit 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 3p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 6p ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 23 (see figure 37) 'c6201b no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? h 2 *h + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # *t 2 t + 1 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid *2 4 *3p + 3 5p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high *2 *4 *3p + 3 *5p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid *l 2 l + 4 *2p + 2 4p + 17 ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp *not production tested. # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 clkx fsx dx dr figure 37. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1

sgus031 april 2000 59 post office box 1443 ? houston, texas 772511443 dmac, timer, power-down timing switching characteristics for dmac outputs (see figure 38) no parameter 'c6201b unit no. parameter min max unit 1 t d(cko1h-dmacv) delay time, clkout1 high to dmac valid *2 10 ns *not production tested. 1 1 clkout1 dmac[0:3] figure 38. dmac timing timing requirements for timer inputs 2 (see figure 39) no 'c6201b unit no. min max unit 1 t w(tinp) pulse duration, tinp high or low *2p ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. *not production tested. switching characteristics for timer outputs (see figure 39) no parameter 'c6201b unit no. parameter min max unit 2 t d(cko1h-toutv) delay time, clkout1 high to tout valid *2 9 ns *not production tested. 2 1 clkout1 tinp tout 2 figure 39. timer timing switching characteristics for power-down outputs (see figure 40) no parameter 'c6201b unit no. parameter min max unit 1 t d(cko1h-pdv) delay time, clkout1 high to pd valid *2 9 ns *not production tested. 1 1 clkout1 pd figure 40. power-down timing

sgus031 april 2000 60 post office box 1443 ? houston, texas 772511443 jtag test-port timing timing requirements for jtag test port (see figure 41) no 'c6201b unit no. min max unit 1 t c(tck) cycle time, tck *50 ns 3 t su(tdiv-tckh) setup time, tdi/tms/trst valid before tck high *10 ns 4 t h(tckh-tdiv) hold time, tdi/tms/trst valid after tck high *5 ns *not production tested. switching characteristics for jtag test port (see figure 41) no parameter 'c6201b unit no. parameter min max unit 2 t d(tckl-tdov) delay time, tck low to tdo valid *0 *15 ns *not production tested. tck tdo tdi/tms/trst 1 2 3 4 2 figure 41. jtag test-port timing

sgus031 april 2000 61 post office box 1443 ? houston, texas 772511443 mechanical data glp (s-cbga-n429) ceramic ball grid array 0,15 1,27 m ? 0,10 20 21 25,40 typ 19 18 16 15 17 13 11 10 12 14 y v w aa u r t n m p 8 7 6 4 5 k h j f e g 3 2 c a b 1 d l 9 seating plane 4164732/a 08/98 sq 27,20 26,80 0,50 0,70 0,60 0,90 1,00 1,22 3,30 max 1,27 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec mo-156 d. flip chip application only e. for 320c6201b (1.8 v core device). f. package weight for glp is 7.65 grams. thermal resistance characteristics (s-cbga package) no c/w air flow 1 r q jc junction-to-case, measured to the bottom of solder ball 3.0 n/a 2 r q jc junction-to-case, measured to the top of the package lid 7.3 n/a 3 r q ja junction-to-ambient 14.5 0 4 11.8 150 fpm 5 r q jma junction-to-moving-air 11.1 250 fpm 6 r q jma junction to moving air 10.2 500 fpm 7 r q jb junction-to-board, measured by soldering a thermocouple to one of the middle traces on the board at the edge of the package 6.2 n/a
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

▲Up To Search▲

Price & Availability of SM320C6201BGLP

	To Download SM320C6201BGLP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .